In November 2018, researchers from the University of California, Santa Barbara presented a paper on CMOS-compatible graphene interconnects. Following this work, a team of University of California Santa Barbara (UCSB) engineering researchers recently came out with a method to utilize nanometer-scale doped multilayer graphene (DMG) interconnects well suited to the mass-production of integrated circuits.
For more than 20 years interconnects have been manufactured using copper as the base material, yet, the limitations of this metal when shrinking it to the nanoscale resistivity increase, which poses a “fundamental threat to the $500 billion semiconductor industry,” say researchers at UCSB. Graphene holds the potential to resolve this issue as a global desire for smarter, faster, lighter and affordable technology and devices continues to expand.
“As you reduce the dimensions of copper wires, their resistivity shoots up,” states Kaustav Banerjee, a professor in the Department of Electrical and Computer Engineering. Resistivity is a material property that is not supposed to change, but at the nanoscale, all properties change.
The UCSB team now believes it has found a promising method to use graphene for interconnects. However, it is not a case of simply replacing copper with graphene in the manufacturing process as research is still being carried out. Therefore, transposing the material from the university or other facility testing environments to high-volume production and wide-spread usage is yet another obstacle that must be overcome.
Professor Banerjee states that the only way the semiconductor industry will move forwards is when, “you find a way to synthesize graphene directly onto silicon wafers.” Issues arise back-end synthesizing after the transistors are fabricated – you face a thermal budget that can’t exceed a temperature of about 500 degrees Celsius.
If the silicon wafer gets too hot during the back-end processes employed to fabricate the interconnects, other elements that are already on the chip may get damaged, or some impurities may start diffusing, changing the characteristics of the transistors
Now, after a pursuit of over a decade, Professor Banerjee’s lab has developed an innovative pressure-assisted solid-phase diffusion method that enables the direct synthesis of high-quality multi-layer graphene compatible with typical standard industry processes for the mass production of integrated circuits. A method that requires the application of pressure and temperature to two materials in close contact so to cause them to diffuse into one another. Thus, overcoming the bottleneck of risking damage or diffusing any impurities to other elements present on the chips and keeping the characteristics of the transistors intact.
The process began with the UCSB team depositing solid-phase carbon in the form of graphite onto a deposited layer of nickel metal of optimized thickness. Then, exposing the graphite powder to heat (about 300 degrees Celsius) and pressure caused disintegration in the graphite. The high diffusivity of carbon in nickel enables it to move quickly through the metal film forming multiple graphene layers as the carbon atoms then recombine on the other surface of the nickel closer to the dielectric substrate.
Junkai Jiang, Lead author of UCSB’s research paper explaining the process, said the lab was able to, “optimize the nickel thickness and other process parameters to obtain precisely the number of graphene layers we want at the dielectric surface”.
“Because our process involves relatively low temperatures that pose no threat to the other fabricated elements on the chip, including the transistors, we can make the interconnects right on top of them,” Mr. Jiang continues. UCSB has since filed a provisional patent on their innovative process, hoping to overcome certain barriers that have so far prevented graphene from replacing copper.
The challenge, according to the researchers, remains in getting tech-giants such as Intel – who produce a vast amount of chips each year with great profits – to accept replacing copper with graphene into its manufacturing process. UCSB’s Banerjee has been in negotiations with industry partners that have demonstrated an interest in licensing the compatible graphene synthesis technology, which could pave the way for what would be the first 2D material to enter the mainstream semiconductor industry.