Researchers from UC Santa Barbara are introducing a new all-graphene integrated circuit design schema. The researchers suggest a fabrication process that starts with a single-layer graphene sheet, then etches it into ribbons (which turn to semiconductors or metals, depends on the width of the ribbons) and finally metal and gate dielectric are deposited and patterned. They say this design may allow much smaller transistors and interconnects than what's possible with silicon transistors and metal interconnects. They hope this design can be realized in the "near future".
One of the big advantages of this process is that it uses just graphene to create both the semiconducting transistors and the metal interfaces. This will result in lower interface/contact resistances. The researchers presented a study with performance evaluation - those circuits achieved a 1.7 times higher signal-to-noise margin and 1-2 decades lower static power consumption over current CMOS technology.