Researches from the University of California, Riverside and University of California, Los Angeles have demonstrated a novel above-IC graphene NEMS switches for electrostatic discharge (ESD) protection applications.
This graphene ESD switch is a two-terminal device with a gap between the conducting substrate at the bottom and a suspended graphene membrane on top serving as the discharging path. This new concept provides a potentially revolutionary mechanism for the on-chip ESD protections.
“Compared with conventional ESD devices based on PN junctions”, said Dr. Qi Chen, author of this study, “The Graphene ESD switch has many advantages, it is a passive mechanical switch, so ideally it has zero leakage and minimum parasitic capacitance; In addition, it shows dual-polarity ESD performance while the PN junction-based devices can only work for single-polarity protection, which can largely reduce the ESD device head counts; Furthermore, graphene shows excellent thermal and mechanical performance; Most importantly, this device can be fabricated at the CMOS backend through 3D heterogeneous integration, instead of taking up large chip areas with core IC”.
The researchers developed a CMOS-compatible process to fabricate the graphene NEMS ESD switches in cleanroom and characterized with the transmission line pulse (TLP). This device shows great promise for future generation on-chip ESD protection applications, according to Qi.
This work was funded by National Science Foundation (NSF).