Researchers from the University of Texas at Austin, in collaboration with Aixtron developed a new method to grow high-quality wafer-scale (300 mm) graphene sheets. This process may enable the integration of graphene with Silicon CMOS and pave the way towards graphene-based electronics.
The method is based on CVD growth on polycrystalline copper film coated silicon substrates. They report that their graphene has better charge carrier transport characteristics compared to previously synthesized poly- or single-crystalline wafers. The graphene has few defects and covers over 96% of the 300-mm wafer substrate.