Sep 26, 2014

Researchers from the University of Texas at Austin, in collaboration with Aixtron developed a new method to grow high-quality wafer-scale (300 mm) graphene sheets. This process may enable the integration of graphene with Silicon CMOS and pave the way towards graphene-based electronics.

The method is based on CVD growth on polycrystalline copper film coated silicon substrates. They report that their graphene has better charge carrier transport characteristics compared to previously synthesized poly- or single-crystalline wafers. The graphene has few defects and covers over 96% of the 300-mm wafer substrate.

As part of the research, the researchers created more than 25,000 G-FET transistors from these films, which means a yield of almost 75% (up from 20% in previous efforts). Around 18% of the devices show a charge mobility of more than 3000 cm2/(Vs), which is more than three times higher than that previously seen in CVD polycrystalline graphene samples.

This process, which is scalable further according to the research, was possible by keeping the temperature and gas distribution uniform during the CVD growth. The Aixtron team used an advanced gas showerhead, as well as multiple thermocouples to accurately balance temperature

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